Title

Design and Implementation of an FPGA-based Processor for Compressed Images

Abstract

This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed.

Department(s)

Electrical and Computer Engineering

Second Department

Computer Science

Keywords and Phrases

Binary Images; Image Coding; Image Compression; Microprocessor Chips

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2000 SPIE -- The International Society for Optical Engineering, All rights reserved.


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