Designing Test Patterns for Effective Measurement of Typical TSV Pairs in a Silicon Interposer

Abstract

In this paper, practical test patterns are designed to calculate the characteristics of Through-Silicon Via (TSV) pairs in a silicon interposer. Proposed test patterns include probing pads, traces and TSVs, which are modeled by a combination of impedances and admittances. Performance of the test patterns is obtained from simulation models built in full wave simulation solver. TSV response is then obtained by de-embedding the pad and trace from the test patterns. The TSV response is also verified by analytical TSV characterization and full wave simulation results for only TSV structures. Thus the paper provides a guide to design feasible test structures from which true response of a TSV pair can be derived.

Meeting Name

2014 International Symposium on Electromagnetic CompatibiIity, EMC 2014 (2014: May 12-16, Tokyo, Japan)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Electromagnetic Compatibility (EMC) Laboratory

Comments

The Institute of Electronics, Information and Communication Engineers, Communications Society (IEICE-CS)

Keywords and Phrases

Electromagnetic compatibility; Electronics packaging; Integrated circuit interconnects; Integrated circuit manufacture; Silicon; analytical; De-embedding; Full-wave simulations; Practical tests; Silicon interposers; Test structure; Through-Silicon-Via (TSV); TSV; Three dimensional integrated circuits

International Standard Book Number (ISBN)

978-488552287-1

International Standard Serial Number (ISSN)

1077-4076

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Dec 2014

Link to Full Text

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