Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling

Abstract

The paper deals with the extraction, from the measurement, of the parameters needed to identify in time domain the hysteretic behavior of the coupling capacitance of through silicon via (TSV). The algorithm is developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the crosstalk among TSV and IC active devices are shown and discussed.

Meeting Name

2016 IEEE International Symposium on Electromagnetic Compatibility (2016: Jul. 25-29, Ottawa, Canada)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Capacitance; Circuit simulation; Electromagnetic compatibility; Electronics packaging; Equivalent circuits; Extraction; Hysteresis; Integrated circuit interconnects; Integrated circuit manufacture; Reconfigurable hardware; Active devices; Dielectric hysteresis; Equivalent circuit model; Nonlinear effect; Signal Integrity; Through silicon vias; Time domain; Three dimensional integrated circuits

International Standard Book Number (ISBN)

978-1-5090-1441-5

International Standard Serial Number (ISSN)

1077-4076

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jul 2016

Link to Full Text

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