Title

Design of On-Chip Linear Voltage Regulator Module and Measurement of Power Distribution Network Noise Fluctuation at High-Speed Output Buffer

Abstract

By applying on-chip linear VRM, PDN inductance is greatly decreased and PDN resonance peak disappears, which is usually generated by PCB/PKG inductance and on-chip capacitance. To confirm, we design an application circuits which have on-chip linear voltage regulator module (VRM) with aggressor and victim buffer. We validate the advantages of on-chip linear VRM by measuring fabricated chip in this research. Moreover, we show PDN self-impedance at output buffer by simulation with designed PCB's S-parameter, and eye-diagram power fluctuation up to 1 Gbps.

Meeting Name

24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (2015: Oct. 25-28, San Jose, CA)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Keywords and Phrases

Capacitance; Electric network analysis; Electronics packaging; Inductance; Organic pollutants; Polychlorinated biphenyls; Scattering parameters; Voltage regulators; Application circuits; Eye diagrams; Linear voltage regulators; On-chip capacitance; On-chip voltage regulator; Power distribution network; Power fluctuations; Power integrity; Chip scale packages

International Standard Book Number (ISBN)

978-1-5090-0040-1

International Standard Serial Number (ISSN)

2165-4107

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Share

 
COinS