Equivalent Circuit Modeling of Dielectric Hysteresis Loops in Through Silicon Vias
Abstract
This paper proposes a numerical solution of the nonlinear equations that describes the hysteretic behavior of the coupling capacitance among through silicon vias in three-dimensional integrated circuits. Behavioral ordinary differential equations are formulated and solved by an equivalent circuit described in SPICE syntax. These results are then compared with those obtained by measurements.
Recommended Citation
S. Piersanti et al., "Equivalent Circuit Modeling of Dielectric Hysteresis Loops in Through Silicon Vias," IEEE Transactions on Electromagnetic Compatibility, vol. 57, no. 6, pp. 1510 - 1516, Institute of Electrical and Electronics Engineers (IEEE), Dec 2015.
The definitive version is available at https://doi.org/10.1109/TEMC.2015.2478849
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Center for High Performance Computing Research
Second Research Center/Lab
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Circuit simulation; Differential equations; Electronics packaging; Hysteresis; Integrated circuit interconnects; Nonlinear equations; Ordinary differential equations; SPICE; Coupling capacitance; Dielectric hysteresis; Equivalent circuit model; Hysteretic behavior; Numerical solution; Through silicon vias; Three dimensional integrated circuits; equivalent circuit; nonlinear circuits; (TSVs); time domain
International Standard Serial Number (ISSN)
0018-9375
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Dec 2015
