Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's resources is an efficient placement and routing mechanism. This paper presents an optimization technique based on swarm intelligence for FPGA placement and routing. Mentor graphics technology mapping netlist file is used to generate initial FPGA placements and routings which are then optimized by particle swarm optimization (PSO). Results for the implementation of a binary coded decimal bidirectional counter and an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.
G. K. Venayagamoorthy and V. G. Gudise, "Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms," Proceedings of the Conference on Evolvable Hardware, 2004. 2004 NASA/DoD, Institute of Electrical and Electronics Engineers (IEEE), Jan 2004.
The definitive version is available at http://dx.doi.org/10.1109/EH.2004.1310813
Conference on Evolvable Hardware, 2004. 2004 NASA/DoD
Electrical and Computer Engineering
Keywords and Phrases
FPGA Placement; FPGA Routing; Xilinx FPGA; Arithmetic Logic Unit; Binary Coded Decimal Bidirectional Counter; Circuit Optimisation; Digital Circuits Implementation; Field Programmable Gate Arrays; Field Programmable Gate Arrays Platforms; Genetic Algorithms; Graphics Technology; Integrated Circuit Layout; Logic Design; Mapping Netlist File; Network Routing; Particle Swarm Optimization; Swarm Intelligence
Article - Conference proceedings
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.