Abstract

An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their self-timed nature. Early Completion performs the completion detection for registration stage i at the input of the register, instead of at the output of the register as in standard NULL Convention Logic. This method requires that the single-rail completion signal from registration stage i+1 , Ko i+1 , be used as an additional input to the completion detection circuitry for registration stage i , to maintain self-timed operation. However, Early Completion does necessitate an assumption of equipotential regions, introducing a few easily satisfiable timing assumptions, thus making the design potentially more delay-sensitive. To illustrate the technique, Early Completion is applied to a case study of an optimally pipelined 4-bit by 4-bit unsigned multiplier utilizing full-word completion, where a speedup of 1.21 is achieved while self-timed operation is maintained and latency remains unchanged.

Meeting Name

IEEE Computer Society Annual Symposium on VLSI, 2002

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Early Completion Technique; NULL Convention Self-Timed Digital Systems; Completion Detection; Delay-Sensitive Design; Equipotential Regions; Full-Word Completion; Latency; Logic Design; Multiplying Circuits; Optimally Pipelined Unsigned Multiplier; Pipeline Processing; Register Input; Registration Stage; Self-Timed Operation; Single-Rail Completion Signal; Speedup; Throughput; Timing; Timing Assumptions

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2002 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Full Text Link

Share

 
COinS