DC power bus decoupling of a multi-layer PCB is modeled by a combination of a lumped circuit model at low frequencies ( < 200 MHz), and a mixed-potential integral equation approach at high frequencies. In order to determine the lumped parameters of via interconnects, an effective procedure using a network analyzer has been developed to characterize the trace/via inductances/resistances. For an 8 inch × 10 inch ten-layer test board used in this study, the simulations show good agreement with the measurement. This method can lead to new design strategies of decoupling for multilayer PCB power buses.
H. Shi et al., "Simulation and Measurement for Decoupling on Multilayer PCB DC Power Buses," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (1996, Santa Clara, CA), pp. 430-435, Institute of Electrical and Electronics Engineers (IEEE), Aug 1996.
The definitive version is available at https://doi.org/10.1109/ISEMC.1996.561273
IEEE International Symposium on Electromagnetic Compatibility (1996: Aug. 19-23, Santa Clara, CA)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Decoupling; Design Strategies; Electric Resistance; Equivalent Circuits; High Frequencies; Inductances; Integral Equations; Low Frequencies; Lumped Circuit Model; Mixed-Potential Integral Equation; Multilayer PCB DC Power Buses; Network Analyzer; Printed Circuit Layout; Printed Circuit Testing; Resistances; Simulations; Via Interconnects; Computer Simulation; Electric Network Analyzers; Electric Power Supplies To Apparatus; Lumped Parameter Networks; Mathematical Models; Multilayers; DC Power Bus Decoupling; Printed Circuit Boards
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Article - Conference proceedings
© 1996 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.