DC power bus decoupling of a multi-layer PCB is modeled by a combination of a lumped circuit model at low frequencies (less than 200 MHz), and a mixed-potential integral equation approach at high frequencies. In order to determine the lumped parameters of via interconnects, an effective procedure using a network analyzer has been developed to characterize the trace/via inductances/resistances. For an 8"x10" ten-layer test board used in this study, the simulations show good agreement with the measurement. This method can lead to new design strategies of decoupling for multilayer PCB power buses
H. Shi et al., "Simulation and Measurement for Decoupling on Multilayer PCB DC Power Buses," Proceedings of the IEEE 1996 International Symposium on Electromagnetic Compatibility, 1996, Institute of Electrical and Electronics Engineers (IEEE), Jan 1996.
The definitive version is available at http://dx.doi.org/10.1109/ISEMC.1996.561273
IEEE 1996 International Symposium on Electromagnetic Compatibility, 1996
Electrical and Computer Engineering
Keywords and Phrases
Decoupling; Design Strategies; Electric Resistance; Equivalent Circuits; High Frequencies; Inductances; Integral Equations; Low Frequencies; Lumped Circuit Model; Mixed-Potential Integral Equation; Multilayer PCB DC Power Buses; Network Analyzer; Printed Circuit Layout; Printed Circuit Testing; Resistances; Simulations; Via Interconnects
Article - Conference proceedings
© 1996 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.