Abstract

In this paper a method is being proposed to find the optimal dimension of Programmable Gate Macro Block (PGMB) in clock-free nanowire crossbar architecture. A PGMB is a nanowire crossbar matrix with discrete number of rows and columns on which the NCL (Null Convention Logic) gates can be programmed. This method uses inherent redundancy to route through defective crosspoints. A 6 X 10 defect-free crossbar can be used to program any of the 27 threshold gates. Due to imperfections and variations in nanoscale manufacturing process, high defect densities are anticipated. Thus, such defects should be located when tested and the logic has to be rerouted around them to maintain proper functionality. This paper discusses this problem and tried to find an optimal solution through simulations. In the final submission, more effective logic mapping techniques will be proposed and validated.

Meeting Name

7th IEEE International Conference on Nanotechnology: IEEE-NANO (2007: Aug. 2-5, Hong Kong, China)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Clock-Free Nanowire Crossbar Architecture; Defect-Avoidance Mapping; Null Convention Logic (NCL); Electric Wire; Industrial Engineering; Nanostructures; Nanotechnology; Nanowires; Quality Assurance; Redundancy; Reliability; Technology; Threshold Logic; Crossbar Architecture; Defect-Free; Discrete Numbers; High Defect Densities; Inherent Redundancy; International Conferences; Logic Mapping; Macro Block; Manufacturing Processes; Nano Scaling; Optimal Solutions; Programmable Gates; Redundancy Optimization; Threshold Gates; Nanostructured Materials

International Standard Book Number (ISBN)

978-1424406074

International Standard Serial Number (ISSN)

1944-9399

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2007

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