Decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of IC/capacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement.
J. Fan et al., "Quantifying Decoupling Capacitor Location," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2000, Washington, D.C.), vol. 2, pp. 761-766, Institute of Electrical and Electronics Engineers (IEEE), Aug 2000.
The definitive version is available at http://dx.doi.org/10.1109/ISEMC.2000.874717
IEEE International Symposium on Electromagnetic Compatibility (2000: Aug. 21-25, Washington, DC)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Printed Circuit Layout; Printed Circuit Testing; Coupled Circuits; DC Machinery; Inductance Measurement; Integral Equations; Integrated Circuits; Location; Surface Mount Technology; Decoupling Capacitors Location; Mutual Inductance; Capacitors; Inductance; Electromagnetic Induction
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Article - Conference proceedings
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