Abstract

Decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of ICkapacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement.

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility, 2000

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Printed Circuit Layout; Printed Circuit Testing

Library of Congress Subject Headings

Capacitors
Electromagnetic induction
Inductance
Integral equations
Surface mount technology

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2000 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Full Text Link

Share

 
COinS