This paper evaluates the quality effectiveness of redundancy utilization in reconfigurable multichip mode (RMCM) systems. Due to reconfigurability, the RMCM system can implement a device with different redundancy levels. A redundancy level is determined by the requirement of fault tolerance (FT) of the device under implementation which can be realized through reconfiguration. No previous work has adequately investigated the effect of utilization of redundancy on the quality-level (QL) of RMCM. In this paper, the tolerance to escape from testing is also introduced to provide more extensive and comprehensive analysis and is referred to as escape tolerance (ET). This can be achieved by utilizing an appropriate amount of redundancy and is exploited for evaluating its effect on the QL of RMCM with different utilizations of redundancy. It is shown through theoretical analysis that the coverage of testing [i.e., fault coverage (FC)] can be improved by reconfiguration. Thus, we derive the QL by relating the QL to the yield enhancement by reconfiguration, the effect of interconnection yield and ET on the QL, and the improvement in FC by reconfiguration. In the proposed approaches, appropriate combinatorial models are formulated to take into account the parameters related to the redundancy and reconfiguration process in RMCM systems. From the extensive parametric simulation results, it is shown that there exists a bound in the effectiveness of redundancy utilization (i.e., the amount of redundancy) depending on the RMCM yield and FC. Using the proposed approach, the redundancy utilization in RMCM systems can be appropriately used to enhance the QL.
M. Choi et al., "Quality Enhancement of Reconfigurable Multichip Module Systems by Redundancy Utilization," IEEE Transactions on Instrumentation and Measurement, Institute of Electrical and Electronics Engineers (IEEE), Jan 2002.
The definitive version is available at http://dx.doi.org/10.1109/TIM.2002.803305
Electrical and Computer Engineering
Keywords and Phrases
FPGA; VLSI; Acceptable Assembly Yield; Combinatorial Models; Escape Tolerance; Fault Coverage; Fault Diagnosis; Fault Tolerance; Field Programmable Gate Arrays; Field-Programmable System; Interconnection Yield; Multichip Modules; Quality Enhancement; Rapid Hardware; Reconfigurable Architectures; Reconfigurable Multichip Module Systems; Redundancy; Redundancy Utilization; Yield Enhancement
International Standard Serial Number (ISSN)
Article - Journal
© 2002 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.