Abstract

Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault model

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

CAM Architecture; CAM Chips; IC Testing; Associative Memories; Content-Addressable Memories; Content-Addressable Storage; Fault Diagnosis; Fault Modeling; Integrated Circuit Testing; Integrated Memory Circuits; Memory Architecture; Testing Strategy

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 1994 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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