Power bus decoupling designs on multilayer printed circuit boards must adequately account for the power bus interplane capacitance and its consequences for the design. Lumped element models for a power bus on a multilayer printed circuit board where an appreciable or entire portion of a layer is devoted to power and ground have been developed. The models are applicable below the distributed resonances of the board. Analytical, circuit simulation, and experimental studies have been conducted to test the models, investigate the effects of the distributed interplane capacitance of the power bus, and the effect of interconnect inductance associated with surface-mount decoupling capacitors.
J. L. Drewniak et al., "Modeling Power Bus Decoupling on Multilayer Printed Circuit Boards," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (1994, Chicago, IL), pp. 456-461, Institute of Electrical and Electronics Engineers (IEEE), Aug 1994.
The definitive version is available at http://dx.doi.org/10.1109/ISEMC.1994.385605
IEEE International Symposium on Electromagnetic Compatibility (1994: Aug. 22-26, Chicago, IL)
Electrical and Computer Engineering
Keywords and Phrases
Capacitance; Circuit Resonance; Electric Network Analysis; Lumped Parameter Networks; Mathematical Models; Printed Circuit Design; Surface Mount Technology; Multilayer Printed Circuit Boards; Power Bus Decoupling; Printed Circuit Boards; EMI; SPICE; SPICE Simulations; Circuit Analysis Computing; Circuit Simulation; Distributed Interplane Capacitance; Distributed Resonances; Electromagnetic Interference; Experimental Studies; Inductance; Interconnect Inductance; Lumped Element Models; Modeling; Power Bus Interplane Capacitance; Printed Circuits; Surface-Mount Decoupling Capacitors
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