Abstract
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the "layout-timing" problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the Locally Synchronous, Globally Asynchronous Design for QCA is proposed in this paper. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design will be possible.
Recommended Citation
M. Choi and N. Park, "Locally Synchronous, Globally Asynchronous Design for Quantum-Dot Cellular Automata (LSGA QCA)," Proceedings of the 5th IEEE Conference on Nanotechnology (2005, Nagoya, Japan), vol. 1, pp. 287 - 290, Institute of Electrical and Electronics Engineers (IEEE), Jul 2005.
The definitive version is available at https://doi.org/10.1109/NANO.2005.1500707
Meeting Name
5th IEEE Conference on Nanotechnology (2005: July 11-15, Nagoya, Japan)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Integrated Circuit Layout; Logic Design; Synchronization; VLSI Circuits; Data Flows; Layout-Timing; Quantum-Dot Cellular Automata; Self-Timed Circuit Design; Automata Theory
International Standard Book Number (ISBN)
978-0780391994
International Standard Serial Number (ISSN)
1944-9399
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2005 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jul 2005
