Abstract
Electrostatic discharge (ESD) generators are used for testing the robustness of electronics towards ESD. Most generators are built in accordance with the IEC 61000-4-2 specifications. It is shown that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprising fast CMOS devices, while rise time and current derivative of the discharge current did not correlate well. The electric parameters are compared for typical and modified ESD generators and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of this paper are discussed with respect to reproducibility and test severity.
Recommended Citation
K. Wang et al., "Impact of ESD Generator Parameters on Failure Level in Fast CMOS System," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, 2003. EMC 2003, Institute of Electrical and Electronics Engineers (IEEE), Aug 2003.
The definitive version is available at https://doi.org/10.1109/ISEMC.2003.1236563
Meeting Name
IEEE International Symposium on Electromagnetic Compatibility, 2003. EMC 2003
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS Integrated Circuits; CMOS Logic Circuits; ESD Generator; Electrostatic Devices; Failure Analysis; Fast CMOS System; Induced Loop Voltage; Integrated Circuit Testing; Electrostatic discharges
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Aug 2003
