Abstract

Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's fixed resources is an efficient placement and routing mechanism. This paper presents particle swarm optimization (PSO) for FPGA placement and routing. Preliminary results for the implementation of an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.

Meeting Name

IEEE Computer society Annual Symposium on VLSI, 2004

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

FPGA; PSO; Xilinx; Arithmetic Logic Unit; Digital Circuits; Field Programmable Gate Arrays; Fixed Resources; Network Routing; Optimisation; Particle Swarm Optimization; Placement Mechanism; Routing Mechanism

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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