Abstract
Particle swarm optimization (PSO) motivated by the social behavior of organisms is proposed for evolution of combinational logic circuits. Results are presented to show that PSO based evolution of digital circuits are equivalent to or even with better solutions (with minimum number of logic gates) than that of a human designer and other genetic algorithm (GA) based techniques. This PSO based approach converges faster than other approaches reported in literature using genetic algorithms and as a result the computational intensity involved in hardware evolution is reduced. Examples taken from the literature are used to evaluate the performance of the proposed PSO approach.
Recommended Citation
G. K. Venayagamoorthy and V. G. Gudise, "Evolving Digital Circuits Using Particle Swarm," Proceedings of the International Joint Conference on Neural Networks, 2003, Institute of Electrical and Electronics Engineers (IEEE), Jan 2003.
The definitive version is available at https://doi.org/10.1109/IJCNN.2003.1223391
Meeting Name
International Joint Conference on Neural Networks, 2003
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Combinational Circuits; Combinatorial Logic Circuit; Computational Intensity; Digital Circuits; Genetic Algorithm; Genetic Algorithms; Hardware Evolution; Human Designer; Particle Swarm Optimization; Social Behavior
International Standard Serial Number (ISSN)
1098-7576
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 2003
