This paper proposes a novel environmental-based method for evaluating the good yield rate (GYR) of systems-on-chip (SoC) during fabrication. Testing and yield evaluation at high confidence are two of the most critical issues for the success of SoC as a viable technology. The proposed method relies on different features of fabrication, which are quantified by the so-called Fabrication environmental parameters (EPs). EPs can be highly correlated to the yield, so they are analyzed using statistical methods to improve its accuracy and ultimately direct the test process to an efficient execution. The novel contributions of the proposed method are: 1) to establish an adequate theoretical foundation for understanding the fabrication process of SoCs together with an assurance of the yield at a high confidence level and 2) to ultimately provide a realistic approach to SoC testing with an accurate yield evaluation. Simulations are provided to demonstrate that the proposed method significantly improves the confidence interval of the estimated yield as compared with existing testing methodologies such as random testing (RT).


Electrical and Computer Engineering

Keywords and Phrases

SOC-Based Instrumentation Systems; SoC Testing; System on a Chip; Defect Level; Environmental-Based Characterization; Fabrication Environmental Parameter (EP); Fabrication Environmental Parameters; Fault Coverage; Good Yield Rate; Integrated Circuit Testing; Integrated Circuit Yield; Random Testing; Statistical Analysis; Statistical Methods; Stratified Testing; System-On-Chip; Test Equipment; Test Process; Yield Evaluation

International Standard Serial Number (ISSN)


Document Type

Article - Journal

Document Version

Final Version

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© 2005 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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