The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges. The most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This issue is commonly referred to as the "layout =timing" problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the locally synchronous, globally asynchronous design for QCA has been recently proposed. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design is be possible. Also, the proposed technique is more scalable in designing large-scale systems. Since a less number of cells is used, the overall area is smaller and the manufacturability is better. In this paper, numerous multi-bit adder designs are considered to demonstrate the layout efficiency and robustness of the proposed globally asynchronous QCA design technique

Meeting Name

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems


Electrical and Computer Engineering

Keywords and Phrases

VLSI; Adders; Asynchronous Circuits; Cellular Automata; Delay Circuits; Delay Insensitive Design; Flexible QCA Circuit Design; Four-Phase Clocking; Integrated Circuit Layout; Layout Efficiency; Locally Synchronous Globally Asynchronous Design; Logic Design; Multi-Bit Adder Designs; Quantum Dots; Quantum Gates; Quantum-Dot Cellular Automata; Self-Timed Circuit Design Technique; Timing

International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

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© 2006 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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