Abstract
The adequacy of the DC power bus decoupling for CMOS devices can be determined if the effective board decoupling capacitance, the CMOS load capacitance, the CMOS power dissipation capacitance, the switching time, and the allowable bus noise voltage are known. A simple method is presented for estimating the effective decoupling capacitance. The load and power dissipation capacitance values are shown analytically and experimentally to be closely related to the transient current. The transient current and switching time are used to estimate the transient noise voltage on the power bus
Recommended Citation
S. Radu et al., "Designing Power Bus Decoupling for CMOS Devices," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, 1998, Institute of Electrical and Electronics Engineers (IEEE), Jan 1998.
The definitive version is available at https://doi.org/10.1109/ISEMC.1998.750120
Meeting Name
IEEE International Symposium on Electromagnetic Compatibility, 1998
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS Devices; CMOS Integrated Circuits; CMOS Load Capacitance; CMOS Power Dissipation Capacitance; Allowable Bus Noise Voltage; Capacitance; Conducted EMI; Effective Board Decoupling Capacitance; Electromagnetic Interference; Parameter Estimation; Power Bus Decoupling Design; Radiated EMI; Switching; Switching Time; Transient Analysis; Transient Current; Transient Noise Voltage Estimation
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 1998 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 1998
