We present various 4-bit× 4-bit unsigned multipliers designed using the delay-insensitive convention logic (NCL) paradigm. They represent bit-serial, iterative, and fully parallel multiplication architectures. NCL is a self-timed logic paradigm in which control is inherent in each datum. NCL follows the so-called weak conditions of Seitz's delay-insensitive signaling scheme. Like other delay-insensitive logic methods, the NCL paradigm assumes that forks in wires are isochronic. NCL uses symbolic completeness of expression to achieve delay-insensitive behavior. Simulation results show a large variance in circuit performance in terms of power, area, and speed. This study serve as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.
S. Smith et al., "Design and Characterization of Convention Self-Timed Multipliers," IEEE Design & Test of Computers, Institute of Electrical and Electronics Engineers (IEEE), Jan 2003.
The definitive version is available at http://dx.doi.org/10.1109/MDT.2003.1246161
Electrical and Computer Engineering
Keywords and Phrases
VLSI; Asynchronous Circuits; Bit-Serial Architecture; Circuit Performance; Circuit Simulation; Clockless Digital VLSI Circuit; Convention Logic; Delay-Insensitive Method; Delay-Insensitive Signaling Scheme; Digital Arithmetic; Iterative Architecture; Logic Design; Multiplying Circuits; Parallel Architectures; Parallel Multiplication Architecture; Self-Timed Multiplier Design
International Standard Serial Number (ISSN)
Article - Journal
© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.