In recent years, crosstalk noise has emerged a serious problem because more and more devices and wires have been packed on electronic chips. As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is the important phenomenon that must be taken into account. Despite of being more immune to crosstalk noise than their ASIC (application specific integrated circuit) counterparts, the dense interconnected structures of FPGAs (field programmable gate arrays) invite more vulnerabilities with crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults affected by crosstalk noise. This paper proposes a new approach for detecting the effects such as glitches and delays in transition that are due to crosstalk noise in FPGAs. This approach is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any overhead for testing.
S. Kakarla and W. K. Al-Assadi, "A Framework for the Detection of Crosstalk Noise in FPGAs," Proceedings of the IEEE Region 5 Technical Conference, 2007, Institute of Electrical and Electronics Engineers (IEEE), Apr 2007.
The definitive version is available at http://dx.doi.org/10.1109/TPSD.2007.4380383
IEEE Region 5 Technical Conference, 2007
Electrical and Computer Engineering
Keywords and Phrases
Field Programmable Gate Arrays; Integrated Cicuit Testing; Integrated Circuit Noise; Logic Testing
Article - Conference proceedings
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