Abstract

In this paper, a two-dimensional (2D) Crank-Nicholason (CN) finite difference time domain (FDTD) method is proposed for VLSI interconnect/substrate characterization. Through rigorous truncation and dispersion error analyses, a guideline on using this technique is presented. Several iterative solvers are investigated to accelerate the solution of the CN-FDTD scheme. Numerical examples are given to demonstrate the accuracy and the efficiency of the proposed algorithm.

Meeting Name

InternationalSymposium on Electromagnetic Compatibility, 2004

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

2D FDTD Method; CN-FDTD Scheme; Crank-Nicholason Method; VLSI; VLSI Interconnect/Substrate Characterization; Dispersion Error Analysis; Finite Difference Time Domain Method; Finite Difference Time-Domain Analysis; Integrated Circuit Interconnections; Integrated Circuit Modelling; Iterative Methods; Iterative Solvers; Truncation Error Analysis; Two-Dimensional FDTD Method

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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