Abstract
I DDQ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I DDQ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I DDQ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared
Recommended Citation
W. K. Al-Assadi et al., "A Bipartite, Differential I DDQ Testable Static RAM Design," Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing, 1995, Institute of Electrical and Electronics Engineers (IEEE), Jan 1995.
The definitive version is available at https://doi.org/10.1109/MTDT.1995.518079
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
SRAM; SRAM Chips; Accuracy; Bipartite Differential I/DDQ/ Testable Static RAM Design; Current Testing; Defect Detection; Fault Activation; Fault Diagnosis; Fault Location; High-Density IC Fault Detection; Integrated Circuit Testing; Memory Partitioning; Off-Line Testing; Parallel Write/Read Operations; Quiescent Power Supply Current Measurement; Static Random Access Memories; System Operational Speed; Test Speed; Testability
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 1995 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 1995
