The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of interconnected primitive devices in a circuit as a gate-level component. This is usually called the subcircuit extraction problem. The paper presents some background on subcircuit extraction. Subcircuit extraction is becoming a more critical issue with the increasing design sizes of very large scale integrated circuits (VLSICs). In the future, one of the most important tasks is to convert current stand-alone subcircuit extraction algorithms into economic benefits. We should make every effort to find those companies who would like to incorporate these algorithms into their VLSI layout verification software to speed up the process.

Meeting Name

12th IEEE International Conference on Fuzzy Systems, 2003


Electrical and Computer Engineering

Second Department

Computer Science

Keywords and Phrases

CMOS Device Dimensions; CMOS Integrated Circuits; VLSI; VLSI Layout Verification Software; Circuit Layout CAD; Computer Aided VLSI Design; Computer Aided Design; Economic Benefits; Integrated Circuit Layout; Layout Analysis; Packing Density; Physical Design Automation; Subcircuit Extraction; Very Large Scale Integrated Circuits

International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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