Abstract

The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.

Meeting Name

International Symposium on Electromagnetic Compatibility, 2004. EMC 2004

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

ESD Scan; Fast CMOS System; Induced Loop Voltage; Susceptibility Map

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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