Balanced Dual- Stage Repair for Dependable Embedded Memory Cores


Advances in revolutionary system-on-chip (SoC) technology mainly depend on the high-performance ultra-dependable system core components. Among those core components, embedded memory system core, currently acquiring 54% of SoC area share, will continue its domination of SoC area share as it is anticipated to approach about 94% of SoC area share by the year 2014. Since memory cells are considered as more prone to defects and faults than logic cells, redundancy and repair have been extensively practiced for enhancing defect and fault tolerance. Unlike in legacy PCB (printed circuit board) or MCM (multichip module) based systems, embedded core components cannot be physically replaced once they are fabricated onto a SoC. To realize enhanced manufacturing yield and field reliability, both ATE (automated test equipment) and BISR (built-in-self-repair) are commonly utilized to allocate redundancy for embedded memory system cores. Since ATE (for repairing manufacturing defects) and BISR (for repairing field faults) share the given redundancy, probabilistic redundancy partitioning and utilization techniques are proposed in this paper to achieve optimal combination of yield and reliability of the embedded memory system core. Parametric simulation results are shown extensively.


Electrical and Computer Engineering

Keywords and Phrases

ATE (Automated Test Equipment); BIST/D/R (Built in Self-Test-Diagnosis and Repair); Embedded Memory Core Repair; Redundancy Balancing; SoC (System-On-Chip) Technology

Document Type

Article - Journal

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