This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).


Electrical and Computer Engineering

Keywords and Phrases

5 GHz; Capacitance; Circuit Noise; Closely Spaced Power-Return Plane Pairs; Digital Circuits; Electromagnetic Compatibility; Embedded Capacitance; High-Speed PCB Designs; High-Speed Digital Designs; Interference Suppression; Layer Stack Ups; Power-Bus Decoupling; Power-Bus Input Impedance Measurements; Power-Bus Noise Measurements; Power-Bus Noise Reduction; Printed Circuit Board Designs; Printed Circuit Design; Printed Circuit Testing; Thin Dielectric Material Layer

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Article - Journal

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Final Version

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© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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