It has been shown that fundamental electronic structures such as Diodes, and FET's can be constructed using selectively doped semiconducting carbon nanotubes or silicon nanowires (CNT's, SiNW's) at nanometer scale. Memory and Logic cores using these technologies have been proposed, that use the configurable junctions in two-dimensional crossbars of CNT's. These memories and logic arrays at this scale exhibit significant amount of defects that account for poor yield. Configuration of these devices in presence of defects demands for an overhead in terms of area and programming time. In this work, we introduce a PLA (programmable logic array) configuration that makes use of design-specific redundancy in terms of number of nanowires, in order to simplify the process of programming the PLA, increase the yield and reduce the time complexity and in turn, the cost of the system.
M. V. Joshi and W. K. Al-Assadi, "Nanofabric PLA Architecture with Double Variable Redundancy," Proceedings of the IEEE Region 5 Technical Conference, 2007, Institute of Electrical and Electronics Engineers (IEEE), Apr 2007.
The definitive version is available at https://doi.org/10.1109/TPSD.2007.4380347
IEEE Region 5 Technical Conference, 2007
Electrical and Computer Engineering
Keywords and Phrases
Carbon Nanotubes; Nanotechnology; Programmable Logic Arrays
Article - Conference proceedings
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