Abstract
The effect of defects within a single cell of a static random access memory (SRAM) is examined. All major types of faults, including bridging, transistor stuck-open and stuck-on, are examined. A significant fraction of all faults cause high IDDQ values to be observed. Faults leading to inter-cell coupling are identified.
Recommended Citation
W. K. Al-Assadi et al., "Modeling of Intra-Cell Defects in CMOS SRAM," Records of the 1993 IEEE International Workshop on Memory Testing, 1993, Institute of Electrical and Electronics Engineers (IEEE), Jan 1993.
The definitive version is available at https://doi.org/10.1109/MT.1993.263145
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS SRAM; CMOS Integrated Circuits; IDDQ Values; SRAM Chips; Bridging; Defects; Fault Location; Fault Models; Intercell Coupling; Intra-Cell Defects; Semiconductor Device Models; Static Random Access Memory; Stuck-On Faults; Transistor Stuck-Open
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 1993 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 1993
