EMI filters are often utilized on I/O lines to reduce high-frequency noise from being conducted or coupled off the PCB and resulting in an EMI problem. However, layout parasitics are usually inevitable in practical circuit design, and the filtering performance may vary. In this study, the impact of the board layout on the filtering performance is investigated by |S21| measurements of sample PCB boards with different filter layouts. The finite-difference time-domain method is applied to model the boards, support the experimental work, and can be used to provide a means for conducting "what-if" engineering studies.
X. Ye et al., "Investigation of PCB Layout Parasitics in EMI Filtering of I/O Lines," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2001, Montreal, Quebec), vol. 1, pp. 501-504, Institute of Electrical and Electronics Engineers (IEEE), Aug 2001.
The definitive version is available at https://doi.org/10.1109/ISEMC.2001.950692
IEEE International Symposium on Electromagnetic Compatibility (2001: Aug. 13-17, Montreal, Quebec)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
What-If Engineering Studies; EMC; EMI; EMI Filters; I/O Lines EMI Filtering; PCB Layout Parasitics; Electromagnetic Compatibility; Electromagnetic Interference; Filtering Performance; Filters; Finite Difference Time-Domain Analysis; Finite-Difference Time-Domain Method; High-Frequency Noise Filtering; Printed Circuit Layout; Printed Circuits; S21 Measurements; Electric Lines; Finite Difference Method; Frequencies; Integrated Circuit Layout; Schematic Diagrams; Signal Filtering And Prediction; Signal Interference; Spurious Signal Noise; Time Domain Analysis; High-Frequency Noise; Printed Circuit Boards
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International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2001 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.