This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous NULL Convention Logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18,um TSMC CMOS process.The multiplier is realized using both static and semi-static Dualversions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.
R. Sankar et al., "Implementation of Static and Semi-Static Versions of a Bit-wise Pipelined Dual-rail NCL 2S Complement Multiplier," Proceedings of the IEEE Region 5 Technical Conference, 2007, Institute of Electrical and Electronics Engineers (IEEE), Jan 2007.
The definitive version is available at https://doi.org/10.1109/TPSD.2007.4380386
IEEE Region 5 Technical Conference, 2007
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
Multiplier; NCL; NULL Convention Logic; Wallace Tree; VHDL (Computer hardware description language)
Article - Conference proceedings
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