Abstract

General methods for reducing printed circuit board (PCB) emissions over a broad band of high frequencies are necessary to meet EMI requirements, as processors become faster and more powerful. One mechanism by which EMI can be coupled off a PCB or multichip module (MCM) structure is from high-frequency fringing electric fields on the DC power and reference planes at the substrate periphery. An approach for EMI mitigation by stitching multiple ground planes together along the periphery of multilayer PCB power-bus stacks with closely spaced vias is reported and quantified in this paper. Power-bus noise induced EMI and coupling from the board edges is the major concern herein. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. Design curves and an empirical equation are extracted from a parametric study to summarize the variation of the radiated EMI as a function of layer thickness and stitch spacing

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

3 M; DC Power Planes; EM Coupling; EMI Mitigation; FDTD Method; HF Electric Fields; MCM; PCB Emissions Reduction; Closely Spaced Vias; Electric Fields; Electromagnetic Coupling; Electromagnetic Interference; Finite Difference Time-Domain Analysis; Finite-Difference Time Domain; High-Frequency Fringing Electric Fields; Interference Suppression; Layer Thickness; Multichip Module; Multichip Modules; Multilayer PCB Power-Bus Stacks; Multilayer Power-Bus Stacks; Multiple Ground Planes; Noise; Power-Bus Noise Induced EMI; Printed Circuit Board Emissions; Printed Circuits; Processors; Radiated EMI; Reference Planes Stitching; Via Stitch Spacing

International Standard Serial Number (ISSN)

0018-9375

Document Type

Article - Journal

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2001 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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