Doctoral Dissertations


Xu Gao

Keywords and Phrases

CMOS integrated circuits; Delay effects; IC immunity; Near-field far-field transformation


"The first topic of this dissertation is far-field prediction using only magnetic near-field scanning. Near-field scanning has been used extensively for the far-field estimation of antennas. Applied to electromagnetic compatibility (EMC) problems, near-field scanning has been used to estimate emissions from both integrated circuits (ICs) and printed circuit boards (PCBs). Interest in applying far-field predictions using near-field to EMI/EMC problems has recently grown. To predict the far-field emissions from a PCB in the top half space, the near-field data on a planar surface above PCB usually is sufficient. However, near-field measurement on only one planar surface may not be enough to predict the far-field radiation of three-dimensional structures. The near-field on an enclosed Huygens's surface may be preferred for near-field scanning when predicting the far-field radiation associated with the EMI problems of some complex structures. Based on the equivalence theorem (Huygens's principle), both equivalent electric current obtained from the tangential magnetic field and equivalent magnetic current obtained from the tangential electric field are needed to perform far-field transformation from near-field data. However, designing electric field probes for tangential components is more difficult than designing magnetic field probes. As a result and in the interest of reducing scan time, far-field transformation based only on magnetic field near-field measurements is preferred. In the first paper, a novel method is proposed to predict the far-field radiation using only the magnetic near-field component on a Huygens's box. The proposed method was verified with two simulated examples and one measurement case. The effect of inaccuracy of magnetic field and the incompleteness of the Huygens's box on far-field results is investigated in this paper. The proposed method can be applied for arbitrary shapes of closed Huygens's surfaces. Only the tangential magnetic field needs to be measured. And it also shows good accuracy and robustness in use. Measuring only the magnetic field cuts the scan time in half. The second topic of this dissertation is modeling delay variations in CMOS digital logic circuits due to electrical disturbances in the power supply. Electronic designers go to considerable effort to minimize the susceptibility of electronic systems against electromagnetic interference. For many systems, the component which fails is an integrated circuit (IC). Susceptibilities are typically found through testing, which is expensive, time consuming, and does not always uncover problems that are encountered in the field. While IC-level testing helps to establish the operational limits of an IC, testing rarely ensures the IC can withstand all interferences, even within the specified limits. Even when a problem is found, the engineer often does not know why a problem was caused or the best way to prevent the problem in the future. Solving problems through trial and error cannot be done as it is at the system level, because of the prohibitive cost of manufacturing and testing multiple versions of the IC. The IC engineer must build the IC to be robust on the first design cycle. IC failures may be caused by a "hard" failure of the IC, for example, due to latch-up or permanent damage to an I/O pin, or may be caused by a "soft" failure, where incorrect data is read from I/O, internal logic, and/or memory. Soft errors that occur within the logic and/or memory components of the IC can be particularly difficult to deal with since errors associated with these components are much more diverse and complex than those associated with I/O. One common reason for soft errors is that a change in the power supply voltage causes a change in the propagation delay through internal logic or the clock tree, so that the clock edge arrives at a register before valid data and an incorrect logic value is stored at the register. While methods are available to predict the level of voltage fluctuation within the IC from an external electromagnetic event, predicting when a failure will occur as a result of the event is challenging. Methods are developed in the second paper and third paper to help predict these soft failures, by predicting the change in the propagation delay through logic during an electromagnetic disturbance of the power supply. In the second paper, an analytical delay model was developed to predict propagation delay variations in logic circuits when the power supply is disturbed by an electromagnetic event. Simulated and measured results demonstrate the accuracy of the approach. Four different types of logic circuits were tested, verifying that the proposed delay model can be applied to a wide range of logic circuits and process technologies. Analytical formulas were developed to predict the clock period variation in integrate circuit when the power supply is disturbed by an electromagnetic event in the third paper. The proposed formulas can be seen as a clock jitter model. The clock jitter due to the power supply variation can be estimated by the proposed propagation delay model. It is more meaningful, however, to estimate the clock period variation rather than the delay variation for one clock edge, because it is clock period which affects if a soft error will happen or not. Simulated results using Cadence Virtuoso demonstrate the validity and accuracy of the proposed approach. Three different types of noise were used to disturb the power supply voltage, verifying that the proposed model can be applied to a wide range of disturbance of power supply. Many electromagnetic events cause soft errors in ICs by momentarily disturbing the power supply voltage. The proposed model can be helpful for predicting and understanding the soft errors caused by these timing changes within the logic"--Abstract, page iv.


Pommerenke, David

Committee Member(s)

Beetner, Daryl G.
Fan, Jun, 1971-
Zhang, Yaojiang
Liu, Xiaoqing Frank


Electrical and Computer Engineering

Degree Name

Ph. D. in Electrical Engineering


Missouri University of Science and Technology

Publication Date

Summer 2014

Journal article titles appearing in thesis/dissertation

  • Far-field prediction using only magnetic near-field scanning for EMI test
  • Modeling delay variations in cmos digital logic circuits due to electrical disturbances in the power supply
  • Clock jitter model for single-ended buffer due to disturbances in the power supply


xi, 90 pages

Note about bibliography

Includes bibliographical references.


© 2014 Xu Gao, All rights reserved.

Document Type

Dissertation - Open Access

File Type




Library of Congress Subject Headings

Electromagnetic interference
Metal oxide semiconductors, Complementary
Electromagnetic waves -- Computer simulation
Near-fields -- Measurement

Thesis Number

T 10530

Electronic OCLC #