"There is a lack of systematic procedures that can be used to find uni-code totally sequential (UTS) assignments from a flow table description of an asynchronous sequential circuit. Presented here is an iterative internal state assignment method. This method consists of three algorithms. The first generates a minimum variable initial assignment from a flow table description. The second tests the validity of this assignment by constructing minimum length transition paths without crossover and the third augments this assignment by adding an internal state variable in the event that all transition paths cannot be constructed without crossover. The second and the third algorithms are used iteratively until a valid non-universal UTS assignment is produced.
The iterative state assignment method is systematic in all its phases. Every phase of the method includes more than one algorithm to perform the same function. The algorithm producing minimum length transition paths is very powerful in that it can also be used in conjunction with other state assignment methods producing either universal or non-universal UTS assignments.
After one obtains a valid UTS assignment an algorithm is provided to replace some or all of the totally sequential transitions with mixed mode transitions. This reduces the number of subtransitions in a given transition path and therefore speeds up the transition time considerably"--Abstract, page ii.
Tracey, James H.
Alcorn, Herbert R., 1933-2008
Stigall, Paul D.
Dekock, Arlan R.
Taylor, Javin M.
Electrical and Computer Engineering
Ph. D. in Electrical Engineering
University of Missouri--Rolla
v, 78 pages
© 1972 Dattatraya Govind Raj-Karne, All rights reserved.
Dissertation - Open Access
Library of Congress Subject Headings
Asynchronous circuits -- Computer-aided design
Electronic circuit design
Print OCLC #
Electronic OCLC #
Link to Catalog Record
Raj-Karne, Dattatraya Govind, "A method for generating UTS assignments with an iterative state transition algorithm" (1972). Doctoral Dissertations. 192.