Doctoral Dissertations

Title

Gate level pipelining optimization, energy estimation, and design for test techniques for asynchronous NULL convention circuits using industry-standard design tools

Keywords and Phrases

NULL Convention Logic circuits

Advisor(s)

Smith, Scott C.

Committee Member(s)

Beetner, Daryl G.
Choi, Minsu
McCracken, Theodore E.
Wilkerson, Ralph W.
Al-Assadi, Waleed K.

Department(s)

Electrical and Computer Engineering

Degree Name

Ph. D. in Computer Engineering

Publisher

University of Missouri--Rolla

Publication Date

Spring 2007

Journal article titles appearing in thesis/dissertation

  • Automated gate-level pipelining for asynchronous NULL convention digital circuits
  • Energy calculation and estimation for delay-insensitive digital circuits
  • DFT techniques and automation for asynchronous NULL conventional logic circuits

Pagination

xi, 105 leaves

Note about bibliography

Includes bibliographical references.

Rights

© 2007 Venkat Raghavan Satagopan, All rights reserved.

Document Type

Dissertation - Citation

File Type

text

Language

English

Library of Congress Subject Headings

Asynchronous circuits
Density functionals
Logic circuits -- Design and construction

Thesis Number

T 9204

Print OCLC #

181104243

Link to Catalog Record

Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.

http://laurel.lso.missouri.edu/record=b6128748~S5

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