Gate level pipelining optimization, energy estimation, and design for test techniques for asynchronous NULL convention circuits using industry-standard design tools
Keywords and Phrases
NULL Convention Logic circuits
Smith, Scott C.
Beetner, Daryl G.
McCracken, Theodore E.
Wilkerson, Ralph W.
Al-Assadi, Waleed K.
Electrical and Computer Engineering
Ph. D. in Computer Engineering
University of Missouri--Rolla
Journal article titles appearing in thesis/dissertation
- Automated gate-level pipelining for asynchronous NULL convention digital circuits
- Energy calculation and estimation for delay-insensitive digital circuits
- DFT techniques and automation for asynchronous NULL conventional logic circuits
xi, 105 leaves
© 2007 Venkat Raghavan Satagopan, All rights reserved.
Dissertation - Citation
Library of Congress Subject Headings
Logic circuits -- Design and construction
Print OCLC #
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.http://laurel.lso.missouri.edu/record=b6128748~S5
Satagopan, Venkat, "Gate level pipelining optimization, energy estimation, and design for test techniques for asynchronous NULL convention circuits using industry-standard design tools" (2007). Doctoral Dissertations. 1741.