A Non-blocking Multithreaded Architecture with Support for Speculative Threads
Abstract
In this paper we provide both a qualitative and a quantitative evaluation of a decoupled multithreaded architecture that uses non-blocking threads. Our architecture is based on simple in-order pipelines and complete decoupling of memory accesses from execution pipelines. We extend the architecture to support thread level speculation using snooping cache coherency protocols. We evaluate the performance gains from speculations by varying the number of load/store instructions compared to computational instructions, miss speculation rates and the degree of thread level speculation. Our architecture presents a viable alternative to complex superscalar and super-speculative CPUs.
Recommended Citation
K. Kavi et al., "A Non-blocking Multithreaded Architecture with Support for Speculative Threads," Lecture Notes in Computer Science, Springer Verlag, Jun 2008.
The definitive version is available at https://doi.org/10.1007/978-3-540-69501-1
Department(s)
Computer Science
Keywords and Phrases
Cache Coherency; Decoupled Architecture; Multithreaded Architectures; Thread Level Speculation
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2008 Springer Verlag, All rights reserved.
Publication Date
01 Jun 2008
