Mixed-Criticality Scheduling upon Varying-Speed Multiprocessors

Abstract

An increasing trend in embedded computing is the moving towards mixed-criticality (MC) systems, in which functionalities of different importance degrees (criticalities) are implemented upon a common platform. Most previous work on MC scheduling focuses on the aspect that different timing analysis tools may result in multiple WCET estimations for each "job" (piece of code). Recently, a different MC model has been proposed, targeting systems with varying execution speeds. It is assumed that the precise speed of the processor upon which the system is implemented varies in an a priori unknown manner during runtime, and estimates must be made as to how low the actual speed may fall. Prior work has dealt with uniprocessor platforms of this kind, the research reported in this paper seeks to generalize this prior work to be applicable to multicore platforms. In our method, a linear program (LP) is constructed based on necessary and sufficient scheduling conditions, and according to its solution, jobs are executed in a processor-sharing based method. Optimality of the algorithm is proved, and an example is constructed to show the necessity of processor sharing.

Meeting Name

2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing, DASC 2014 (2014: Aug. 24-27, Dalian, China)

Department(s)

Computer Science

Keywords and Phrases

Embedded Computing; Importance Degrees; Mixed Criticalities; Multi Processor Scheduling; Multi-Core Platforms; Optimal; Processor Sharing; Varying Speed System

International Standard Book Number (ISBN)

978-147995079-9

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2014

Link to Full Text

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