Diagnosing Single Faults in Fanout-Free Combinational Circuits
We show how to construct, in a simple manner, a test set having n + 1 tests for a fanout-free combinational circuit with n primary inputs which distinguishes (diagnoses) nonequivalent single faults. This result is an improvement over the upper bound in [1, Theorem 3.9] of n + g (g is the number of primary input gates) and the upper bound in [3, Theorem 4],  of 2n for the least number of tests required to distinguish among nonequivalent single faults.
G. Markowsky, "Diagnosing Single Faults in Fanout-Free Combinational Circuits," IEEE Transactions on Computers, vol. C-28, no. 11, pp. 863-864, Institute of Electrical and Electronics Engineers (IEEE), Nov 1979.
The definitive version is available at https://doi.org/10.1109/TC.1979.1675266
Keywords and Phrases
Logic Circuits; Combinatorial; Algorithm; Diagnosing Single Faults; Fanout-free Combinatorial Circuits; Stuck Line Fault; Test Set
International Standard Serial Number (ISSN)
Article - Journal
© 1979 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.