Title

Diagnosing Single Faults in Fanout-Free Combinational Circuits

Abstract

We show how to construct, in a simple manner, a test set having n + 1 tests for a fanout-free combinational circuit with n primary inputs which distinguishes (diagnoses) nonequivalent single faults. This result is an improvement over the upper bound in [1, Theorem 3.9] of n + g (g is the number of primary input gates) and the upper bound in [3, Theorem 4], [5] of 2n for the least number of tests required to distinguish among nonequivalent single faults.

Department(s)

Computer Science

Keywords and Phrases

Logic Circuits; Combinatorial; Algorithm; Diagnosing Single Faults; Fanout-free Combinatorial Circuits; Stuck Line Fault; Test Set

International Standard Serial Number (ISSN)

0018-9340

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 1979 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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