The Weighted Syndrome Sums Approach to VLSI Testing

Abstract

With the advent of VLSI, testing has become one of the most costly, complicated, and time consuming problems. The method of syndrome- testing is applicable toward VLSI testing since it does not require test generation and fault simulation. It can also be considered as a vehicle for self-testing. In order to employ syndrome-testing in VLSI, we electronically partition the chip into macros in test mode. The macros are then syndrome tested in sequence.
In this paper we show the means to syndrome-test macros. We examine the size of the syndrome driver counter and establish a method of determining its minimal length. The problem of minimizing the number of syndrome references needed for testing is also investigated. It is shown that it is always possible to use one weighted syndrome sum as reference for each and every macro. The question of weighted sum syndrome-testability is addressed and methods to achieve it are discussed. A self-test architecture based on these concepts is described.

Department(s)

Computer Science

Keywords and Phrases

Integrated Circuits - Very Large Scale Integration; Integrated Circuit Testing; Partitioning; Self-testing; Syndrome-testable Design; Syndrome-testing

International Standard Serial Number (ISSN)

0018-9340

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 1981 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Dec 1981

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