Abstract

This paper presents a cost error measurement scheme and relaxed synchronization method, for simulated annealing on a distributed memory multicomputer, which predicts the amount of cost error that an algorithm will tolerate. An adaptive error control method is developed and implemented on an Intel iPSC/2

Department(s)

Computer Science

Keywords and Phrases

Intel IPSC/2; Adaptive Error Control Method; Cost Error Measurement Scheme; Distributed Memory Multicomputer; Distributed Memory Systems; Distributed Simulated Annealing; Error Correction Codes; Parallel Algorithms; Relaxed Synchronization Method; Simulated Annealing; Synchronisation; Synchronization

International Standard Serial Number (ISSN)

1045-9219

Document Type

Article - Journal

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 1995 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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