PVD TiN hardmask for Copper Metallization
Abstract
With shrinking geometries and adoption of lower k dielectrics and thinner barriers to minimize device RC delay, there is a need for advanced patterning schemes. Hardmask technology is on demand as the photoresist(PR) films used in semiconductor fabrication need to be thinner to etch sub-45 nm devices. Hardmask films provide high etch selectivity to low-k dielectrics and photoresist, serve as an anti-reflective coating, allowing partial via etch approach and eliminating ULK damage caused by the resist ash strip process. We have optimized PVD TiN process through hardware, process modifications to meet all the requirements of hardmask technology. We also present preliminary etch rate data and via profiles demonstrating the benefits of TiN hardmask. Further work to characterize adhesion and electrical performance is underway.
Recommended Citation
Z. Xie et al., "PVD TiN hardmask for Copper Metallization," Proceedings of the International Symposium on Semiconductor Manufacturing (2007, Santa Clara, CA), Institute of Electrical and Electronics Engineers (IEEE), Oct 2007.
The definitive version is available at https://doi.org/10.1109/ISSM.2007.4446856
Meeting Name
International Symposium on Semiconductor Manufacturing, ISSM 2007 (2007: Oct. 15-17, Santa Clara, CA)
Department(s)
Civil, Architectural and Environmental Engineering
Keywords and Phrases
Atherosclerosis; Tin; Copper; Metallization; Etching; Semiconductor films; Resists; Geometry; Dielectric devices; Delay
International Standard Book Number (ISBN)
978-1-4244-1141-2
International Standard Serial Number (ISSN)
1523-553X
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
17 Oct 2007
