Missouri S&T Scholar's Mine Research RepositoryMissouri S&T Research
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Author: Al-Assadi, Waleed K.

1993  1994  1995  2005  2007  2008  2009 

2009  TOP

Title Author(s)
Design for test of asynchronous NULL convention logic (NCL) circuitsAl-Assadi, Waleed K.; Kakarla, Sindhu;

2008  TOP

Title Author(s)
Analysis and modeling of substrate noise in domino CMOS circuitsGosavi, S.; Al-Assadi, Waleed K.; Burugapalli, S.; Gosavi, Abhijit;
A BIST approach for configurable nanofabric arraysJoshi, Mandar V.; Al-Assadi, Waleed K.;
A BIST technique for configurable nanofabric arraysAl-Assadi, Waleed K.; Joshi, Mandar V.; Chaudhry, Ghulam M.;
Design and FPGA prototyping of a flood prediction systemGandla, Sandeep; Al-Assadi, Waleed K.; Sedighsarvestani, Sahra; Rao, Raghu A. R.;
Design and implementation of FPGA configuration logic block using asynchronous semi-static NCL circuitsDugganapally, Indira P.; Al-Assadi, Waleed K.; Pillai, Vijay; Smith, Scott;
Design and implementation of FPGA configuration logic block using asynchronous static NCLDugganapally, I. P.; Al-Assadi, Waleed K.; Tammina, T.; Smith, S.;
Modeling of substrate noise effects in dynamic CMOS circuitsGosavi, S. R.; Al-Assadi, Waleed K.; Burugapalli, S.;
Nanowire crossbar PLA with adaptive variable redundancyJoshi, M. V.; Al-Assadi, Waleed K.;
Secured hardware design - an overviewBurugapalli, S.; Al-Assadi, Waleed K.;
Testing of asynchronous NULL conventional logic (NCL) circuitsKakarla, S.; Al-Assadi, Waleed K.;

2007  TOP

Title Author(s)
Analysis and modeling of crosstalk noise in domino CMOS circuitsSharma, V.; Al-Assadi, Waleed K.;
DFT techniques and automation for asynchronous NULL conventional logic circuitsSatagopan, V.; Bhaskaran, B.; Al-Assadi, Waleed K.; Smith, S. C.; Kakarla, S.;
A framework for the detection of crosstalk noise in FPGAsKakarla, S.; Al-Assadi, Waleed K.;
Implementation of static and semi-static versions of a 24+8x8 quad-rail NULL convention multiply and accumulate unitSankar, R.; Kadiyala, V.; Bonam, R.; Kumar, S.; Mohan, S.; Kacani, F.; Al-Assadi, Waleed K.; Smith, S. C.;
Implementation of static and semi-static versions of a bit-wise pipelined dual-rail NCL 2S complement multiplierSankar, R.; Kadiyala, V.; Bonam, R.; Kumar, S.; Mohan, S.; Kacani, F.; Al-Assadi, Waleed K.; Smith, S. C.;
Nanofabric PLA architecture with double variable redundancyJoshi, M. V.; Al-Assadi, Waleed K.;
NCL implementation of dual-rail 2S complement 8×8 Booth2 multiplier using static and semi-static primitivesJoshi, M. V.; Gosavi, S.; Jegadeesan, V.; Basu, A.; Jaiswal, S.; Al-Assadi, Waleed K.; Smith, S. C.;
Teaching asynchronous digital design in the undergraduate computer engineering curriculumSmith, S. C.; Al-Assadi, Waleed K.;

2005  TOP

Title Author(s)
Design for test methodology for the IBM PowerPC™ 440 embedded coreAl-Assadi, Waleed K.; Dick, T.A.;
Implementation of design for test for asynchronous NCL designsBhaskaran, B.; Satagopan, V.; Al-Assadi, Waleed K.; Smith, S.C.;

1995  TOP

Title Author(s)
A bipartite, differential I DDQ testable static RAM designAl-Assadi, Waleed K.; Jayasumana, A.P.; Malaiya, Y.K.;

1994  TOP

Title Author(s)
Data-feedthrough faults in circuits using unclocked storage elementsAl-Assadi, Waleed K.; Lu, D.; Jayasumana, A.P.; Malaiya, Y.K.; Tong, C.Q.;
On fault modeling and testing of content-addressable memoriesAl-Assadi, Waleed K.; Jayasumana, A.P.; Malaiya, Y.K.;

1993  TOP

Title Author(s)
Faulty behavior of storage elements and its effects on sequential circuitsAl-Assadi, Waleed K.; Malaiya, Y.K.; Jayasumana, A.P.;
Modeling of intra-cell defects in CMOS SRAMAl-Assadi, Waleed K.; Malaiya, Y.K.; Jayasumana, A.P.;
Use of storage elements as primitives for modeling faults in synchronous sequential circuitsAl-Assadi, Waleed K.; Malaiyat, Y.K.; Jayasumana, A.P.;